1. Technical Field
This disclosure relates to memory devices and more particularly to stacked memory device bus structures.
2. Description of the Related Art
Recent advances in manufacturing capability has allowed memory device manufacturers to begin creating devices in which individual memory device die are stacked one on top of the other. More particularly, to allow the signals from a top die to be routed to a bus or other interface at the bottom of the stack, a technique referred to as through silicon vias (TSV) is used. There are various ways of implementing TSV, but the basic concept is that holes are created through each die from one side to the other, and the holes are metallized. When the dice are aligned and mechanically bonded, a die-to-die electrical pathway (or bus) is created from each signal on the top die all the way through all of the dice to a contact pad on the bottom surface of the bottom die. The die-to-die connections may be made using a bump process, for example. Some advantages of using stacked devices are the lead lengths are more uniform and shorter than typical circuit board traces. Accordingly, memory bus speed may be increased with less signal distortion. However, a disadvantage of using a TSV flow during manufacturing is added cost. Thus, it would desirable for memory architectures that use the TSV flow to have a higher return on investment. However, in some cases, such as in systems that use a wide memory bus, for example, if the bandwidth of such a bus structure does not scale as memory chips are added to the memory system, the cost of manufacturing may outweigh the benefit of using the stacked devices.